• ISO 10918-1 compliant
• Optimized for Xilinx Spartan and Virtex FPGA
• Baseline Encoder
• 8 bit or 12 bit / pixel input
• 8x8 block format pixel input
• Up to 16 components
• Up to 4 Quantization tables
• Up to 8 Huffman tables (four DC and four AC)

Block diagramm of the encoder:

• Predefined luminance and chrominance tables
• Fully synchronous design
• Fully stall able design
• Simple CPU interface for table reprogramming
• Different clocks for encoder and CPU interface
• Single clock cycle per pixel encoding
• No pause cycles between blocks
• Up to 145 MHz operation

Description

Size

Download

Produkt specification JE100 and JE110

PDF, 25 KB

V3.0

Produkt specification JE150 and JE160

PDF, 25 KB

V3.0

Users Manual for JE100, JE110, JE150 and JE160

PDF, 400 KB

V3.0

JE100 8 bit / sample precision for Spartan-II(E) and Virtex(E)

Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 600 KB

V3.0

JE110 8 bit / sample precision for Spartan-III and Virtex-II(P)

Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 360 KB

V3.0

JE150 12 bit / sample precision for Spartan-II(E) and Virtex(E)

Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 1050 KB

V3.0

JE160 12 bit / sample precision for Spartan-III and Virtex-II(P)

Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 430 KB

V3.0