• ISO 10918-1 compliant
• Optimized for Xilinx Spartan and Virtex FPGA
• Baseline Encoder
• 8 bit or 12 bit / pixel input
• Line by line pixel input
• 8 bit Monochrome
• 16 bit Color (YCbCr 4:2:2)
• Up to 4096 pixel per row

Block diagramm of the encoder:

• Simple CPU interface for table reprogramming
• 2 Quantization tables
• 2 fixed Huffman tables (two DC and two AC)
• Fully synchronous design
• Fully stall able design
• Single clock cycle per pixel encoding
• No pause cycles between blocks
• Up to 150 MHz operation

Description

Size

Download

Produkt specification JE200 and JE210

PDF, 21 KB

V3.0

Produkt specification JE250 and JE260

PDF, 21 KB

V3.0

Users Manual for JE200, JE210, JE250 and JE260

PDF, 350 KB

V3.0

JE200 8 bit / sample precision for Spartan-II(E) and Virtex(E)

Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 750 KB

V3.0

JE210 8 bit / sample precision for Spartan-III and Virtex-II(P)

Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 490 KB

V3.0

JE250 12 bit / sample precision for Spartan-II(E) and Virtex(E)

Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 1200 KB

V3.0

JE260 12 bit / sample precision for Spartan-III and Virtex-II(P)

Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprozessor and a C++ class for JPEG file generation.

ZIP, 580 KB

V3.0