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Stand Alone JPEG Baseline Encoder
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- Simple CPU interface for table reprogramming
- 2 Quantization tables
- 2 fixed Huffman tables (two DC and two AC)
- Fully synchronous design
- Fully stall able design
- Single clock cycle per pixel encoding
- No pause cycles between blocks
- Up to 150 MHz operation
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Download
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Product Specifications
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Size
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Download
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JE300 and JE310 cores: 8 bit samples precision for Xilinx architecture.
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PDF, 21 KB
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V3.0
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JE301 and JE302 cores: 8 bit samples precision for Lattice architecture.
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PDF, 29 KB
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V0.5
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JE303 core: 8 bit samples precision for Altera architecture.
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PDF, 29 KB
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V0.5
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JE350 and JE360 cores: 12 bit samples precision for Xilinx architecture.
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PDF, 22 KB
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V3.0
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User Manuals
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Size
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Download
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Users Manual for JE300, JE310, JE350 and JE360
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PDF, 350 KB
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V3.0
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Evaluation Cores
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Size
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Download
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JE300 8 bit / sample precision for Spartan-II(E) and Virtex(E)
Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprocessor and a C++ class for JPEG file generation.
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ZIP, 830 KB
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V3.0
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JE310 8 bit / sample precision for Spartan-III and Virtex-II(P)
Free demo core NGC-file for evaluation, quality reduced to 4 bit, a VHDL Example for core using as coprocessor and a C++ class for JPEG file generation.
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ZIP, 550 KB
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V3.0
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JE350 12 bit / sample precision for Spartan-II(E) and Virtex(E)
Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprocessor and a C++ class for JPEG file generation.
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ZIP, 1326 KB
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V3.0
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JE360 12 bit / sample precision for Spartan-III and Virtex-II(P)
Free demo core NGC-file for evaluation, quality reduced to 6 bit, a VHDL Example for core using as coprocessor and a C++ class for JPEG file generation.
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ZIP, 654 KB
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V3.0
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Xilinx, Virtex and Spartan are registered Trademarks of Xilinx, Inc.
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