•  For Xilinx and Altera FPGAs, or as VHDL
•  Parallel compression of 4 unsynchronized images
•  Marker generation included
•  Block building RAM included
•  JPEG file output
•  Compliant with Baseline ISO/IEC 10918-1
•  Motion-JPEG capability
• Monochrome or Color (YCbCr 4:2:2)

Block diagramm of the encoder:

• Up to 2048 samples per row
• Baseline encoder
• 8-bit/sample input
• Line by line sample input
• 2 Quantization tables, reprogrammable
• 4 fixed Huffman tables (two DC and two AC)
• Fully synchronous design
• Single clock cycle per sample encoding

Product Specifications

Size

Download

JE430 for Xilinx architecture.

PDF, 25 KB

V0.9

JE440 for Altera architecture.

PDF, 25 KB

V0.9

JE490 Device independent VHDL sourc code.

PDF, 25 KB

V0.9

User Manuals

Size

Download

Users Manual for JE430, JE440 and JE490

PDF, 141 KB

V1.0